1. Field of the Invention
The present invention relates to interconnection structures of packages and fabrication methods thereof, and more particularly, to a low-cost interconnection structure having photosensitive and patternable dielectric layers and a fabrication method thereof.
2. Description of Related Art
Conventionally, a multi-layer conductive trace structure of an integrated circuit is formed by dry-etching a metal layer and then filling it with a dielectric layer. Alternatively, a damascene process may be used, which involves etching a dielectric layer to form a pattern and then filling the pattern with a metal material so as to form conductive traces. As such, the damascene process eliminates the need to etch a metal layer. If the metal layer is made of copper instead of aluminum, the damascene process is preferably used since dry etching of copper is difficult.
Generally, there are two kinds of damascene processes: single and dual. In a dual damascene process, both vias and conductive traces are formed at once through only one metal filling step. The dual damascene process has become increasingly important in semiconductor processes.
FIGS. 1A to 1I are schematic cross-sectional views illustrating a conventional dual damascene process.
Referring to FIG. 1A, a silicon substrate 10 is provided.
Referring to FIG. 1B, a first nitride layer 11, a first oxide layer 12, a second nitride layer 13 and a second oxide layer 14 are sequentially formed on a surface of the silicon substrate 10 by chemical vapor deposition (CVD).
Referring to FIG. 1C, a patterned first photoresist layer 15 is formed on the second oxide layer 14.
Referring to FIG. 1D, the second nitride layer 13 and the second oxide layer 14 are etched by using the first photoresist layer 15 as an etching mask.
Referring to FIG. 1E, the first photoresist layer 15 is removed.
Referring to FIG. 1F, a patterned second photoresist layer 16 is formed on the second oxide layer 14.
Referring to FIG. 1G, the first nitride layer 11 and the first oxide layer 12 are etched by using the second photoresist layer 16 as an etching mask, thereby forming vias 171 and grooves 172 in the first nitride layer 11, the first oxide layer 12, the second nitride layer 13 and the second oxide layer 14.
Referring to FIG. 1H, the second photoresist layer 16 is removed.
Referring to FIG. 1I, a metal layer 18 is deposited in the vias 171 and the grooves 172 and a portion of the metal layer 18 higher than the top surface of the second oxide layer 14 is removed so as to form conductive vias 181 and a conductive trace layer 182.
However, the above-described CVD, photoresist coating, exposure and development and dry etching steps are complicated, costly and time-consuming Particularly, the CVD and dry-etching steps are performed under a high vacuum environment in combination with special gases, thereby greatly increasing the process time and cost.
Therefore, there is a need to develop a technique for overcoming the above-described disadvantages.